Investigation of Program Efficiency Overshoot in 3D Vertical Channel NAND Flash with Randomly Distributed Traps

Author:

Park Chanyang1ORCID,Yoon Jun-Sik1ORCID,Nam Kihoon1ORCID,Jang Hyundong1ORCID,Park Minsang2ORCID,Baek Rock-Hyun1ORCID

Affiliation:

1. Department of Electrical Engineering, Pohang University of Science and Technology (POSTECH), Pohang 37673, Republic of Korea

2. SK hynix Inc., Icheon 17336, Republic of Korea

Abstract

The incremental step pulse programming slope (ISPP) with random variation was investigated by measuring numerous three−dimensional (3D) NAND flash memory cells with a vertical nanowire channel. We stored multiple bits in a cell with the ISPP scheme and read each cell pulse by pulse. The excessive tunneling from the channel to the storage layer determines the program efficiency overshoot. Then, a broadening of the threshold voltage distribution was observed due to the abnormal program cells. To analyze the randomly varying abnormal program behavior itself, we distinguished between the read variation and over−programming in measurements. Using a 3D Monte−Carlo simulation, which is a probabilistic approach to solve randomness, we clarified the physical origins of over−programming that strongly influence the abnormal program cells in program step voltage, and randomly distributed the trap site in the nitride of a nanoscale 3D NAND string. These causes have concurrent effects, but we divided and analyzed them quantitatively. Our results reveal the origins of the variation and the overshoot in the ISPP, widening the threshold voltage distribution with traps randomly located at the nanoscale. The findings can enhance understanding of random over−programming and help mitigate the most problematic programming obstacles for multiple−bit techniques.

Funder

POSTECH

the National Research Foundation of Korea

Institute of Information & communications Technology Planning & Evaluation

the Ministry of Trade, Industry & Energy

Publisher

MDPI AG

Subject

General Materials Science,General Chemical Engineering

Reference40 articles.

1. Choi, E.-S., and Park, S.-K. (2012, January 10–13). Device considerations for high density and highly reliable 3D NAND flash cell in near future. Proceedings of the IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA.

2. Jang, J., Kim, H.-S., Cho, W., Cho, H., Kim, J., Shim, S.I., Jang, Y., Jeong, J.-H., Son, B.-K., and Kim, D.W. (2009, January 15–17). Vertical cell array using TCAT (Terabit Cell Array Transistor) technology for ultra high density NAND flash memory. Proceedings of the IEEE Symposium on VLSI Technology, Kyoto, Japan.

3. Katsumata, R., Kito, M., Fukuzumi, Y., Kido, M., Tanaka, H., Komori, Y., Ishiduki, M., Matsunami, J., Fujiwara, T., and Nagata, Y. (2009, January 15–17). Pipe-shaped BiCS flash memory with 16 stacked layers and multi-level-cell operation for ultra high density storage devices. Proceedings of the IEEE Symposium on VLSI Technology, Kyoto, Japan.

4. Tanaka, H., Kido, M., Yahashi, K., Oomura, M., Katsumata, R., Kito, M., Fukuzumi, Y., Sato, M., Nagata, Y., and Matsuoka, Y. (2007, January 12–14). Bit cost scalable technology with punch and plug process for ultra high density flash memory. Proceedings of the IEEE Symposium on VLSI Technology, Kyoto, Japan.

5. Lee, S., Lee, Y.-T., Han, W.-K., Kim, D.-H., Kim, M.-S., Moon, S.-H., Cho, H.C., Lee, J.-W., Byeon, D.-S., and Lim, Y.-H. (2004, January 15–19). A 3.3 V 4 Gb four-level NAND flash memory with 90 nm CMOS technology. Proceedings of the IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA.

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