A Picosecond Delay Generator Optimized by Layout and Routing Based on FPGA

Abstract

A delay generator is a timing control device that can generate a delay for the input signal according to the actual requirements. A delay generator with a combination of rough delay and precise delay is implemented on a Xilinx Kintex-7 series FPGA with a design scheme based on carry delay chain. The delay generator uses the delay time parameters sent by the upper monitor to work and to reflect the current working state to the upper monitor. In this article, a theoretical model of the delay generator is designed, and a delay compensation scheme is proposed to make the working state of the theoretical model closer to the actual circuit. Through simulation experiments, the time resolution of the delay generator is 54 ps, and the time accuracy is less than 50 ps. The delay scheme adopted in this article is highly scalable, and the time resolution and time accuracy can be further improved. Finally, a theoretical model of the delay generator with relatively high time resolution is implemented through low resource occupancy rate and little workload.