Using a Voltage Domain Programmable Technique for Low-Power Management Cell-Based Design-Reference-Cited by-同舟云学术

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Using a Voltage Domain Programmable Technique for Low-Power Management Cell-Based Design

Published:2011-09-14 Issue:2 Volume:1 Page:303-326
ISSN:2079-9268
Container-title:Journal of Low Power Electronics and Applications
language:en
Short-container-title:JLPEA

Author:

Cheng Ching-Hwa

Publisher

MDPI AG

Subject

Electrical and Electronic Engineering

Link

http://www.mdpi.com/2079-9268/1/2/303/pdf

Reference6 articles.

1. A dynamic voltage scaled microprocessor system;Burd;IEEE J. Solid State Circuits,2000

2. ULS: A dual-Vth/high-κ nano-CMOS universal level shifter for system-level power management;Mohanty;ACM J. Emerg. Technol. Comput.,2010

3. A dual voltage-frequency VLSI chip for image watermarking in DCT domain;Mohanty;IEEE Trans. Circuits Syst. II,2006

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2. Experimental Efficiency Evaluation of Stacked Transistor Half-Bridge Topologies in 14 nm CMOS Technology;Electronics;2021-05-12

3. Digitalized-Management Voltage-Domain Programmable Mechanisms for Dual-Vdd Low-Power Embedded Digital Systems;2019 IEEE 22nd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS);2019-04

4. Module Based Floorplanning Methodology to Satisfy Voltage Island and Fixed Outline Constraints;Electronics;2018-11-15

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