Secure ECDSA SRAM-PUF Based on Universal Single/Double Scalar Multiplication Architecture

Author:

Zhang Jingqi1ORCID,Chen Zhiming1ORCID,He Xiang1ORCID,Liu Kuanhao1ORCID,Hao Yue1ORCID,Ma Mingzhi2,Wang Weijiang13,Dang Hua1,Li Xiangnan4

Affiliation:

1. School of Integrated Circuits and Electronics, Beijing Institute of Technology, Beijing 100081, China

2. UNISOC (Shanghai) Technology Co., Ltd., Shanghai 201203, China

3. BIT Chongqing Institute of Microelectronics and Microsystems, Chongqing 401332, China

4. School of Information and Electronics, Beijing Institute of Technology, Beijing 100081, China

Abstract

Physically unclonable functions (PUFs) are crucial for enhancing cybersecurity by providing unique, intrinsic identifiers for electronic devices, thus ensuring their authenticity and preventing unauthorized cloning. The SRAM-PUF, characterized by its simple structure and ease of implementation in various scenarios, has gained widespread usage. The soft-decision Reed–Muller (RM) code, an error correction code, is commonly employed in these designs. This paper introduces the design of an RM code soft-decision attack algorithm to reveal its potential security risks. To address this problem, we propose a soft-decision SRAM-PUF structure based on the elliptic curve digital signature algorithm (ECDSA). To improve the processing speed of the proposed secure SRAM-PUF, we propose a custom ECDSA scheme. Further, we also propose a universal architecture for the critical operations in ECDSA, elliptic curve scalar multiplication (ECSM), and elliptic curve double scalar multiplication (ECDSM) based on the differential addition chain (DAC). For ECSMs, iterations can be performed directly; for ECDSMs, a two-dimensional DAC is constructed through precomputation, followed by iterations. Moreover, due to the high similarity of ECSM and ECDSM data paths, this universal architecture saves hardware resources. Our design is implemented on a field-programmable gate array (FPGA) and an application-specific integrated circuit (ASIC) using a Xilinx Virtex-7 and an TSMC 40 nm process. Compared to existing research, our design exhibits a lower bit error rate (2.7×10−10) and better area–time performance (3902 slices, 6.615 μs ECDSM latency).

Funder

Chongqing Natural Science Foundation

Publisher

MDPI AG

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