Characteristics of Cracking Failure in Microbump Joints for 3D Chip-on-Chip Interconnections under Drop Impact

Abstract

With the rapid development of microelectronics packaging and integration, the failure risk of micro-solder joints in packaging structure caused by impact load has been increasingly concerning. However, the failure mechanism and reliability performance of a Cu-pillar-based microbump joint can use little of the existing research on board-level solder joints as reference, due to the downscaling and joint structure evolution. In this study, to investigate the cracking behavior of microbump joints targeted at chip-on-chip (CoC) stacked interconnections, the CoC test samples were subjected to repeated drop tests to reveal the crack morphology. It was found that the crack causing the microbump failure first initiated at the interface between the intermetallic compound (IMC) layer and the solder, propagated along the interface for a certain length, and then deflected into the solder matrix. To further explore the crack propagation mechanism, stress intensity factor (SIF) of the crack tip at the interface between IMC and solder was calculated by contour integral method, and the effects of solder thickness and crack length were also quantitatively analyzed and combined with the crack deflection criterion. By combining the SIF with the fracture toughness of the solder–Ni interface and the solder matrix, a criterion for crack deflecting from the original propagating path was established, which can be used for prediction of critical crack length and deflection angle for the initiation of crack deflection. Finally, the relationship between solder thickness and critical deflection length and deflection angle of main crack was verified by a board level drop test, and the influence of grain structure in solder matrix on actual failure lifetime was briefly discussed.