Research on an Intelligent Test Method for Interconnect Resources in an FPGA

Author:

Xie Weikun1,Qi Wenjing2,Lin Xiaohui3,Wang Houjun1

Affiliation:

1. School of Automation Engineer, University of Electronic and Technology of China, Chengdu 611731, China

2. Shenzhen Institute for Advanced Study, University of Electronic and Technology of China, Shenzhen 518110, China

3. The 58th Research Institute of China Electronics Technology Group Corporation, Wuxi 214072, China

Abstract

With the rapid development of integrated circuit production technology, the scale of FPGA circuits has expanded to billions of gates. The complexity of the internal resource structures in the FPGAs (field programmable gate arrays) is continually increasing, and there is an increasing possibility of various faults in these circuits, especially in interconnect resources. These occupy more than 80% of a chip’s area and have the highest fault rate. To ensure the reliability of the FPGAs, it is very important to perform high-coverage testing on the interconnect resources within them. This article uses AMD Xilinx’s Kintex-7 series FPGA as the research object and proposes a deep-priority algorithm based on graph-based models and improved priority algorithms to intelligently wire the FPGA interconnected resources. The routing results were produced using a configuration script written in the XDL language, and the FPGA configuration and testing were conducted accordingly. This approach achieved a high coverage and intelligent testing for the interconnect resources in the FPGAs.

Publisher

MDPI AG

Subject

Fluid Flow and Transfer Processes,Computer Science Applications,Process Chemistry and Technology,General Engineering,Instrumentation,General Materials Science

Reference18 articles.

1. Insight into a Generic Interconnect Resource Model for Xilinx Virtex and Spartan Series FPGAs;Ruan;IEEE Trans. Circuits Syst. II Express Briefs,2013

2. Toutounchi, S., and Lai, A. (2002, January 7–10). FPGA test and coverage. Proceedings of the International Test Conference, Baltimore, MD, USA.

3. Liao, Y., Ruan, A., Wang, Y., Xiang, C., Wang, L., Huang, H., and Zhu, J. (2011, January 16–19). Interconnect resources testing and faults diagnosis in field programmable gate arrays. Proceedings of the IEEE 2011 10th International Conference on Electronic Measurement & Instruments, Chengdu, China.

4. Niamat, M.Y., Nambiar, R., and Jamali, M.M. (2002, January 4–7). A BIST scheme for testing the interconnects of SRAM-based FPGAs. Proceedings of the The 2002 45th Midwest Symposium on Circuits and Systems, 2002. MWSCAS-2002, Tulsa, OK, USA.

5. Stroud, C., Nall, J., Lashinsky, M., and Abramovici, M. (2002, January 7–10). BIST-based diagnosis of FPGA interconnect. Proceedings of the International Test Conference, Baltimore, MD, USA.

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