1. Insight into a Generic Interconnect Resource Model for Xilinx Virtex and Spartan Series FPGAs;Ruan;IEEE Trans. Circuits Syst. II Express Briefs,2013
2. Toutounchi, S., and Lai, A. (2002, January 7–10). FPGA test and coverage. Proceedings of the International Test Conference, Baltimore, MD, USA.
3. Liao, Y., Ruan, A., Wang, Y., Xiang, C., Wang, L., Huang, H., and Zhu, J. (2011, January 16–19). Interconnect resources testing and faults diagnosis in field programmable gate arrays. Proceedings of the IEEE 2011 10th International Conference on Electronic Measurement & Instruments, Chengdu, China.
4. Niamat, M.Y., Nambiar, R., and Jamali, M.M. (2002, January 4–7). A BIST scheme for testing the interconnects of SRAM-based FPGAs. Proceedings of the The 2002 45th Midwest Symposium on Circuits and Systems, 2002. MWSCAS-2002, Tulsa, OK, USA.
5. Stroud, C., Nall, J., Lashinsky, M., and Abramovici, M. (2002, January 7–10). BIST-based diagnosis of FPGA interconnect. Proceedings of the International Test Conference, Baltimore, MD, USA.