Abstract
Current computation architectures rely on more processor-centric design principles. On the other hand, the inevitable increase in the amount of data that applications need forces researchers to design novel processor architectures that are more data-centric. By following this principle, this study proposes an area-efficient Fast Fourier Transform (FFT) processor through in-memory computing. The proposed architecture occupies the smallest footprint of around 0.1 mm 2 inside its class together with acceptable power efficiency. According to the results, the processor exhibits the highest area efficiency ( FFT / s / area ) among the existing FFT processors in the current literature.
Subject
Electrical and Electronic Engineering,Mechanical Engineering,Control and Systems Engineering
Reference52 articles.
1. Processing data where it makes sense: Enabling in-memory computation;Mutlu;Microprocess. Microsyst.,2019
2. Big data needs a hardware revolution
3. Enabling the Adoption of Processing-in-Memory: Challenges, Mechanisms, Future Research Directions;Ghose;arXiv,2018
4. Scalable processors in the billion-transistor era: IRAM
Cited by
15 articles.
订阅此论文施引文献
订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献