Inhibited Channel Potential of 3D NAND Flash Memory String According to Transient Time
-
Published:2023-02-24
Issue:5
Volume:13
Page:2909
-
ISSN:2076-3417
-
Container-title:Applied Sciences
-
language:en
-
Short-container-title:Applied Sciences
Author:
Cho Taeyoung1, Kim Hyunju1, Kang Myounggon1ORCID
Affiliation:
1. Department of Electronics Engineering, Korea National University of Transportation, Room No. 326, Smart ICT Building, 50 Daehak-ro, Chungju-si 27469, Chungbuk, Republic of Korea
Abstract
The channel potential of natural local self-boosting (NLSB) effects in 16-layer 3D NAND flash memory was analyzed according to transient time. After a program pulse was applied to the selected word line (WL) of the inhibited string channel, the channel potential of the selected WL increased owing to NLSB. The channel potential of the selected WL, increased by NLSB, was analyzed as a function of the threshold voltage (Vth) of the adjacent cell and according to the change in time. The analysis confirmed that the channel potential value decreased gradually over time. However, it was confirmed that the rate at which the channel potential decreases was different depending on the Vth of the adjacent cell. The number of electrons in nitride is different for each Vth. These electrons affect the holes of the spacer and channel. The analysis also confirmed that the movement of electrons was caused by the difference in the hole concentration in the spacer and channel.
Funder
National R&D Program through the National Research Foundation of Korea Basic Science Research Program through the National Research Foundation of Korea
Subject
Fluid Flow and Transfer Processes,Computer Science Applications,Process Chemistry and Technology,General Engineering,Instrumentation,General Materials Science
Reference18 articles.
1. Threedimensional NAND flash architecture design based on single-crystalline stacked array;Kim;IEEE Trans. Electron Devices,2011 2. A 128 Gb 3b/cell V-NAND Flash Memory With 1 Gb/s I/O Rate;Jeong;IEEE J. Solid-State Circuits,2016 3. Jang, J., Kim, H.S., Cho, W., Cho, H., Kim, J., Shim, S.I., Jeong, J.H., Son, B.K., Kim, D.W., and Shim, J.J. (2009, January 15–17). Vertical cell array using TCAT(Terabit Cell Array Transistor) technology for ultra-high density NAND flash memory. Proceedings of the 2009 Symposium on VLSI Technology, Kyoto, Japan. 4. A new programming method to alleviate the program speed variation in three-dimensional stacked array NAND flash memory;Kim;J. Semicond. Technol. Sci.,2014 5. Jeong, M.-K., Joe, S.-M., Jo, B.-S., Kang, H.-J., Bae, J.-H., Han, K.-R., Choi, E., Cho, G., Park, S.-K., and Park, B.-G. (2012, January 10–13). Characterization of traps in 3-D stacked NAND flash memory devices with tubetype poly-Si channel structure. Proceedings of the 2012 International Electron Devices Meeting, San Francisco, CA, USA.
Cited by
1 articles.
订阅此论文施引文献
订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
|
|