RETRACTED: Express Data Processing on FPGA: Network Interface Cards for Streamlined Software Inspection for Packet Processing

Author:

Pradeep Sunkari1ORCID,Sharma Yogesh2ORCID,Verma Chaman3ORCID,Sreeram Gutha4,Hanumantha Rao Panugati4

Affiliation:

1. Department of Computer Science and Engineering, Malla Reddy Engineering College for Women (UGC)–Autonomous Institution Maisammaguda, Secunderabad 500100, Telangana, India

2. Department of Computer Science and Engineering, Koneru Lakshmaiah Education Foundation, Vaddeswaram, Guntur 522302, Andhra Pradesh, India

3. Department of Media & Educational Informatics, Faculty of Informatics, Eotvos Lornad University, 1053 Budapest, Hungary

4. Department of Computer Science and Engineering, Vignana Bharathi Institute of Technology, Aushapur, Ghatkesar, Hyderabad 501301, Telangana, India

Abstract

Modern computers’ network interface cards (NICs) are undergoing changes in order to handle greater data rates and assist with scaling problems caused by general-purpose CPU technology. The inclusion of programmable accelerators to the NIC’s data channel is one of the ongoing improvements that is particularly intriguing since it gives the accelerator the chance to take on a portion of the CPU’s network packet processing duties. Accelerators are frequently developed using platforms like field-programmable gate arrays because packet processing operations have severe latency requirements (FPGAs). When implementing packet processing activities, FPGAs’ gain for through put is the number of data packets being successfully sent per second and latency is the actual time those packets take. However, due to their restricted resources, programming may need to be shared throughout a variety of applications. We provide hXDP, a software solution for FPGAs that targets the Linux eXpress Data Path and performs packet processing functions outlined with the eBPF technology. While maintaining performance on par with top-tier CPUs, hXDP only uses a tiny portion from the field programmable gate arrays, which are semiconductor devices that are based around a matrix of configuration logic blocks (CLB) connected over programmable interconnects. However, we demonstrate that when aiming towards a purpose-built FPGA architecture, many extended Berkeley packet filters (eBPF) allow programmers to use Berkeley packet filter byte code that makes use of certain kernel resources and instruction set architecture, to collocate and even eliminate, with considerably productivity and effectiveness. On an FPGA NIC, we implement hXDP and test its effectiveness using authentic eBPF programmes from the real world. Our version consumes 15% of the FPGA resources and operates at 156.25 MHz. This can constantly change and lead to the act of identification, inspection, extraction, and manipulation so that a network may make more intelligent management decisions.

Publisher

MDPI AG

Subject

Artificial Intelligence,Applied Mathematics,Industrial and Manufacturing Engineering,Human-Computer Interaction,Information Systems,Control and Systems Engineering

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