Review of Analog-To-Digital Conversion Characteristics and Design Considerations for the Creation of Power-Efficient Hybrid Data Converters
Author:
Publisher
MDPI AG
Subject
Electrical and Electronic Engineering
Link
http://www.mdpi.com/2079-9268/8/2/12/pdf
Reference86 articles.
1. A 16-mW 8-Bit 1-GS/s Digital-Subranging ADC in 55-nm CMOS
2. A 40-mW 7-bit 2.2-GS/s Time-Interleaved Subranging CMOS ADC for Low-Power Gigabit Wireless Communications
3. A 32 mW 1.25 GS/s 6b 2b/Step SAR ADC in 0.13$\ \mu$m CMOS
4. A 2.8 GS/s 44.6 mW Time-Interleaved ADC Achieving 50.9 dB SNDR and 3 dB Effective Resolution Bandwidth of 1.5 GHz in 65 nm CMOS
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