Ant Colony Algorithm for Energy Saving to Optimize Three-Dimensional Bonding Chips’ Thermal Layout

Abstract

The thermal effect and heat dissipation have a significant impact on three-dimensional stacked chips, and the positional layout of the chip’s three-dimensional layout directly affects the internal temperature field. One effective way is to plan the overall layout of three-dimensional integrated circuits by considering the thermal effect and layout utilization. In this paper, an ant colony algorithm is used to search for the most planned paths and achieve the overall layout optimization by considering the effects of power, temperature, and location on the thermal layout and using feedback optimization of pheromone concentration. The simulation results show that the optimization of the thermal layout of 3D integrated circuits can be well realized by adjusting the algorithm parameters. The maximum temperature, temperature gradient, and layout scheme verify reliability and practicability. It improves the utilization rate of chips, optimizes the layout, realizes energy conservation, and reduces resource waste.