Hardware Implementation and Performance Study of Analog PIλDμ Controllers on DC Motor

Abstract

In this paper, the performance of an analog PI λ D μ controller is done for speed regulation of a DC motor. The circuits for the fractional integrator and differentiator of PI λ D μ controller are designed by optimal pole-zero interlacing algorithm. The performance of the controller is compared with another PI λ D μ controller—in which the fractional integrator circuit employs a solid-state fractional capacitor. It can be verified from the results that using PI λ D μ controllers, the speed response of the DC motor has improved with reduction in settling time ( T s ), steady state error (SS error) and % overshoot (% M p ).