Research on Electro-Optic Hybrid Multidigit Digital Multiplier Based on Surface Plasmon Polariton Technology

Abstract

Digital multipliers are the core components of digital computers, and improving the speed of transistor electronic computers during computation has almost reached its limit, with high power consumption. In this paper, we proposed an electro-optic hybrid multidigit digital multiplier based on SPP technology, which has the advantages of high speed and low power consumption in optical logic, as well as flexible electrical operation and easy storage. The electro-optic hybrid digital multiplier mainly consists of an electrical AND logic gate, an electro-optic hybrid half adder, and an electro-optic hybrid full adder. The optical logic unit is controlled by activated ITO materials to achieve optical-domain operations, and then the multiplication calculation results are converted into electrical signals through photoelectric conversion. The experimental results show that when the scale is 64 × 64 bits, compared with transistor digital multiplication, the energy consumption is reduced by 48.8%; the speed is increased by a factor of 28; and the volume of the electro-optic hybrid digital multiplier device is larger than that of the transistor multiplier, saving 59.9% of the area. For optical transmission loss, a single adder outputs 0.31 dB at different device scales, while the carry output continuously increases with device scale. At scales of 8 × 8 bits, 16 × 16 bits, and 64 × 64 bits, the insertion losses at the sum output ports are 1.03 dB/μm and 1.87 dB/μm, respectively.