A Cost-Effective Solution to Improving the Electrical Performance of Metal Contacting Interfaces in IC System under Temperature-Humidity Environment

Abstract

Temperature-humidity (TH) induced failure mechanism (FM) of metal contacting interfaces in integrated circuit (IC) systems has played a significant role in system reliability issues. This paper focuses on central processing unit (CPU)/motherboard interfaces and studies several factors that are believed to have a great impact on TH performance. They include: Enabling load, surface finish quality, and contacting area. Test vehicles (TVs) of Clarkdale package and of Ibex peak motherboard were designed to measure low level contact resistance (LLCR) for catching any failure. Several sets of design of experiments (DOE) were conducted on 85°C/85% relative humidity and test results were analyzed. A proposal that correlates asperity spots and contact tip design with contact resistance was proposed and thus a cost-effective solution for improving electrical performance under TH was deduced. The proposal has proven to be reasonably effective in practice.