A Parametric Study of the Effects of Critical Design Parameters on the Performance of Nanoscale Silicon Devices

Abstract

The current electronics industry has used the aggressive miniaturization of solid-state devices to meet future technological demands. The downscaling of characteristic device dimensions into the sub-10 nm regime causes them to fall below the electron–phonon scattering length, thereby resulting in a transition from quasi-ballistic to ballistic carrier transport. In this study, a well-established Monte Carlo model is employed to systematically investigate the effects of various parameters such as applied voltage, channel length, electrode lengths, electrode doping and initial temperature on the performance of nanoscale silicon devices. Interestingly, from the obtained results, the short channel devices are found to exhibit smaller heat generation, with a 2 nm channel device having roughly two-thirds the heat generation rate observed in an 8 nm channel device, which is attributed to reduced carrier scattering in the ballistic transport regime. Furthermore, the drain contacts of the devices are identified as critical design areas to ensure safe and efficient performance. The heat generation rate is observed to increase linearly with an increase in the applied electric field strength but does not change significantly with an increase in the initial temperature, despite a marked reduction in the electric current flowing through the device.