High-Resolution Digital-to-Time Converter Implemented in an FPGA Chip-Reference-Cited by-同舟云学术

High-Resolution Digital-to-Time Converter Implemented in an FPGA Chip

Published:2017-01-04 Issue:1 Volume:7 Page:52
ISSN:2076-3417
Container-title:Applied Sciences
language:en
Short-container-title:Applied Sciences

Author:

Wang Hai,Zhang Min^ORCID,Liu Yan

Publisher

MDPI AG

Subject

Fluid Flow and Transfer Processes,Computer Science Applications,Process Chemistry and Technology,General Engineering,Instrumentation,General Materials Science

Link

http://www.mdpi.com/2076-3417/7/1/52/pdf

Reference14 articles.

1. A UWB Impulse-Radio Timed-Array Radar With Time-Shifted Direct-Sampling Architecture in 0.18-$\mu{\rm m}$ CMOS

2. Low-jitter wide-range integrated time interval/delay generator based on combination of period counting and capacitor charging

3. Multiple Channel Programmable Timing Generators With Single Cyclic Delay Line

4. FPGA Vernier Digital-to-Time Converter With 1.58 ps Resolution and 59.3 Minutes Operation Range

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2. High precision low jitter pulse generator implemented with FPGA transceiver;Measurement;2024-05

3. Implementation of a Time-to-Digital Converter Inside FPGA;2023 IEEE 12th International Conference on Intelligent Data Acquisition and Advanced Computing Systems: Technology and Applications (IDAACS);2023-09-07

4. Review of FPGA-Based Digital-to-Time Converters;2023 IEEE 16th International Conference on Electronic Measurement & Instruments (ICEMI);2023-08-09

5. Linearized 9-Bit Hybrid LBDD PWM Modulator for Digital Class-BD Amplifier;International Journal of Electronics and Telecommunications;2023-07-26