Crosstalk Analysis of Delay-Insensitive Code in High-Speed Package Interconnects

Abstract

The development of integrated circuits has increased the size of chip interconnects, which has brought challenges to interconnect design in chip packages. The closer the spacing between interconnects, the higher the space utilization, which can cause severe crosstalk problems in high-speed circuits. In this paper, we applied delay-insensitive coding to the design of high-speed package interconnects. We also analyzed the effect of delay-insensitive coding on crosstalk improvement in package interconnects at 26 GHz for its high crosstalk immunity. Compared to the synchronous transmission circuit, the 1-of-2 and 1-of-4 encoded circuits designed in this paper can reduce crosstalk peaks by 22.9% and 17.5% on average at a wiring spacing of 1–7 μm, which can achieve closer wiring spacing.