A Performance Optimized CSTBT with Low Switching Loss

Abstract

A novel Performance Optimized Carrier Stored Trench Gate Bipolar Transistor (CSTBT) with Low Switching Loss has been proposed. By applying a positive DC voltage to the shield gate, the carrier storage effect is enhanced, the hole blocking capability is improved and the conduction loss is reduced. The DC biased shield gate naturally forms inverse conduction channel to speed up turn-on period. Excess holes are conducted away from the device through the hole path to reduce turn-off loss (Eoff). In addition, other parameters including ON-state voltage (Von), blocking characteristic and short circuit performance are also improved. Simulation results demonstrate that our device exhibits a 35.1% and 35.9% decrease in Eoff and turn-on loss (Eon), respectively, in comparison with the conventional shield CSTBT (Con-SGCSTBT). Additionally, our device achieves a short-circuit duration time that is 2.48 times longer. In high-frequency switching applications, device power loss can be reduced by 35%. It should be noted that the additional DC voltage bias is equivalent to the output voltage of the driving circuit, enabling an effective and feasible approach towards high-performance power electronics applications.