An Improved SPWM Strategy for Effectively Reducing Total Harmonic Distortion

Abstract

In the inverter circuit, the speed at which the MOSFET is impacted by the presence of a parasitic inductor within the printed circuit board (PCB) leads to a delay in the switching process. Furthermore, the parasitic inductor within the circuit can easily form an LC oscillation with the parasitic capacitor of the MOSFET. These two issues result in an inconsistency between the actual output of the MOSFET and the driving signal waveform, leading to distortion in the sinusoidal pulse width modulation (SPWM) waveform and an increase in total harmonic distortion (THD). It is a common practice to mitigate gate oscillation by introducing a resistor at the gate of the MOSFET. However, elevating the resistance leads to deceleration in the charging process of the MOSFET’s parasitic capacitor, consequently causing an increase in the switching delay, and thereby increasing THD. Therefore, an effective strategy to reduce THD is proposed in this paper, while augmenting the gate resistance, computing the MOSFET switching delay, and applying corrective compensation. In this way, the inherent issues of the switch are addressed, resulting in inverter output waveforms that closely resemble sine waves and reduced THD. Through a combination of simulation and empirical experimentation, the efficacy of the proposed approach in significantly reducing THD in the inverter’s output waveform has been empirically substantiated.