Leakage Power Attack-Resilient Design: PMOS-Reading 9T SRAM Cell

Abstract

Non-invasive side-channel attacks (SCAs) based on leakage power analysis (LPA) have received more attention recently, since leakage current has gradually become more dominant with further scaled technologies. For SRAM cells, LPA exploits the correlation between data in memory cells and their corresponding leakage power. This paper proposes a novel SRAM design in 7 nm node for countering LPA attacks, based on a single-ended PMOS-reading 9T (nine-transistor) cell design. The leakage current imbalance, delay, stability, and robustness of SRAM cells are examined for the proposed memory cell architecture with layout designs, and results are compared against other SRAM cell designs. Simulation results and failure of LPA attacks in case studies confirm the enhanced resilient behavior for the new SRAM cell design.