A Novel Turbo Detector Design for a High-Speed SSVEP-Based Brain Speller

Abstract

The past decade has witnessed the rapid development of brain-computer interfaces (BCIs). The contradiction between communication rates and tedious training processes has become one of the major barriers restricting the application of steady-state visual-evoked potential (SSVEP)-based BCIs. A turbo detector was proposed in this study to resolve this issue. The turbo detector uses the filter bank canonical correlation analysis (FBCCA) as the first-stage detector and then utilizes the soft information generated by the first-stage detector and the pool of identified data generated during use to complete the second-stage detection. This strategy allows for rapid performance improvements as the data pool size increases. A standard benchmark dataset was used to evaluate the performance of the proposed method. The results show that the turbo detector can achieve an average ITR of 130 bits/min, which is about 8% higher than FBCCA. As the size of the data pool increases, the ITR of the turbo detector could be further improved.