A Gate-Level Information Leakage Detection Framework of Sequential Circuit Using Z3
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Published:2022-12-16
Issue:24
Volume:11
Page:4216
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ISSN:2079-9292
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Container-title:Electronics
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language:en
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Short-container-title:Electronics
Author:
Zhang QizhiORCID, Liu Liang, Yuan Yidong, Zhang Zhe, He JiajiORCID, Gao Ya, Li Yao, Guo Xiaolong, Zhao Yiqiang
Abstract
Hardware intellectual property (IP) cores from untrusted vendors are widely used, raising security concerns for system designers. Although formal methods provide powerful solutions for detecting malicious behaviors in hardware, the participation of manual work prevents the methods from reaching practical applications. For example, Information Flow Tracking (IFT) represents a powerful approach to preventing leakage of sensitive information. However, existing IFT solutions either introduce hardware overheads or lack practical automatic working procedures, especially for hardware sequential logic. To alleviate these challenges, we propose a framework that fully automates information leakage detection at the gate level of hardware. This framework introduces Z3, an SMT solver, to automatically check the violation of confidentiality. On the other hand, an automatic tool is developed to remove the manual workload further. In this tool, the gate level hardware is converted to the formal model firstly, and the integrity of the model is assessed. Along with the model converting step, the property for leakage detection is generated as well. The proposed solution is tested on 25 gate-level netlist benchmarks, where sequential designs are included to validate the effectiveness. As a result, Trojans leaking information from circuit outputs can be automatically detected. The measured time consumption of the entire working procedure validates the efficiency of the proposed approach.
Funder
Beijing Smart-Chip Microelectronics Technology Co., Ltd.
Subject
Electrical and Electronic Engineering,Computer Networks and Communications,Hardware and Architecture,Signal Processing,Control and Systems Engineering
Reference36 articles.
1. Agrawal, D., Baktir, S., Karakoyunlu, D., Rohatgi, P., and Sunar, B. (2007, January 20–23). Trojan detection using IC fingerprinting. Proceedings of the 2007 IEEE Symposium on Security and Privacy (SP ’07), Oakland, CA, USA. 2. Jin, Y., and Makris, Y. (2008, January 9). Hardware Trojan detection using path delay fingerprint. Proceedings of the 2008 IEEE International Workshop on Hardware-Oriented Security and Trust, Anaheim, CA, USA. 3. Zhang, X., and Tehranipoor, M. (2011, January 5–6). Case study: Detecting hardware trojans in third-party digital ip cores. Proceedings of the 2011 IEEE International Symposium on Hardware-Oriented Security and Trust, San Diego, CA, USA. 4. Proof-carrying hardware intellectual property: A pathway to trusted module acquisition;Love;IEEE Trans. Inf. Forensics Secur.,2012 5. Jin, Y., Yang, B., and Makris, Y. (2013). Cycle-accurate information assurance by proof-carrying based signal sensitivity tracing. IEEE Int. Symp. Hardw.-Oriented Secur. Trust (HOST), 99–106.
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