A BIST Scheme for Dynamic Comparators-Reference-Cited by-同舟云学术

A BIST Scheme for Dynamic Comparators

Published:2022-12-13 Issue:24 Volume:11 Page:4169
ISSN:2079-9292
Container-title:Electronics
language:en
Short-container-title:Electronics

Author:

Tang Xiao-Bin,Tachibana Masayoshi

Abstract

This paper proposes a built-in self-test (BIST) scheme for detecting catastrophic faults in dynamic comparators. In this scheme, a feedback loop is designed using the characteristics of the comparator; monitoring the voltage in the feedback loop can determine the presence of a circuit fault. The proposed BIST scheme and the circuit under testing are realized at the transistor level. The proposed BIST scheme was simulated using HSPICE. The simulated fault coverage is approximately 87.8% with 90 test circuits. To further verify the effectiveness of the proposed BIST scheme, six faults were injected into the real circuit. The test results were consistent with the simulation results.

Funder

JSPS KAKENHI

Publisher

MDPI AG

Subject

Electrical and Electronic Engineering,Computer Networks and Communications,Hardware and Architecture,Signal Processing,Control and Systems Engineering

Link

https://www.mdpi.com/2079-9292/11/24/4169/pdf

Reference11 articles.

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