Accurate On-Chip Thermal Peak Detection Based on Heuristic Algorithms and Embedded Temperature Sensors
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Published:2023-07-06
Issue:13
Volume:12
Page:2978
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ISSN:2079-9292
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Container-title:Electronics
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language:en
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Short-container-title:Electronics
Author:
Touati Djallel Eddine1ORCID, Oukaira Aziz2ORCID, Hassan Ahmad2ORCID, Ali Mohamed2ORCID, Lakhssassi Ahmed1ORCID, Savaria Yvon2ORCID
Affiliation:
1. Department of Engineering and Computer Science, Université du Québec en Outaouais, Gatineau, QC J9A 1L8, Canada 2. Electrical Engineering Department, Polytechnique Montréal, Montreal, QC H3T 1J4, Canada
Abstract
The reliability and lifetime of systems-on-chip (SoCs) are being seriously threatened by thermal issues. In modern SoCs, dynamic thermal management (DTM) uses the thermal data captured by thermal sensors to constantly track the hot spots and thermal peak locations in real time. Estimating peak temperatures and the location of these peaks can play a crucial role for DTM systems, as temperature underestimation can cause SoCs to fail and have shortened lifetime. In this paper, a novel sensor allocation algorithm (called thermal gradient tracker, TGT), based on the recursive elimination of regions that likely do not contain any thermal peaks, is proposed for determining regions that potentially contain thermal peaks. Then, based on an empirical source temperature detection technique called GDS (gradient direction sensor), a hybrid algorithm for detecting the position and temperature of thermal peaks is also proposed to increase the accuracy of temperature sensing while trying to keep the number of thermal sensors to a minimum. The essential parameters, H and R, of the GDS technique are determined using an automated search algorithm based on simulated annealing. The proposed algorithm has been applied in a system-on-chip (SoC) in which four heat sources are present, and for temperatures ranging between 45 °C and 115 °C, in a chip area equal to 25 mm2. The simulation results show that our proposed sensor allocation scheme can detect on-chip peaks with a maximum error of 1.48 °C and an average maximum error of 0.49 °C by using 15 thermal sensors.
Subject
Electrical and Electronic Engineering,Computer Networks and Communications,Hardware and Architecture,Signal Processing,Control and Systems Engineering
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1. Enhancing Thermal Security of 3D-SiP Systems through Thermal Digital Twin (TDT);2024 IEEE Canadian Conference on Electrical and Computer Engineering (CCECE);2024-08-06 2. Analytical and Numerical Modeling of the Thermal Performance of 3D System-in-Package (SiP);2023 International Conference on Electrical, Computer and Energy Technologies (ICECET);2023-11-16
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