An Efficient Hardware Architecture with Adjustable Precision and Extensible Range to Implement Sigmoid and Tanh Functions

Abstract

The efficient and precise hardware implementations of tanh and sigmoid functions play an important role in various neural network algorithms. Different applications have different requirements for accuracy. However, it is difficult for traditional methods to achieve adjustable precision. Therefore, we propose an efficient-hardware, adjustable-precision and high-speed architecture to implement them for the first time. Firstly, we present two methods to implement sigmoid and tanh functions. One is based on the rotation mode of hyperbolic CORDIC and the vector mode of linear CORDIC (called RHC-VLC), another is based on the carry-save method and the vector mode of linear CORDIC (called CSM-VLC). We validate the two methods by MATLAB and RTL implementations. Synthesized under the TSMC 40 nm CMOS technology, we find that a special case AR∣VR(3,0), based on RHC-VLC method, has the area of 4290.98 μm2 and the power of 1.69 mW at the frequency of 1.5 GHz. However, under the same frequency, AR∣VC(3) (a special case based on CSM-VLC method) costs 3196.36 μm2 area and 1.38 mW power. They are both superior to existing methods for implementing such an architecture with adjustable precision.