A Capacitorless Flipped Voltage Follower LDO with Fast Transient Using Dynamic Bias

Abstract

The output capacitorless low-dropout regulator (OCL-LDO) has developed rapidly in recent years. This paper presents a flipped voltage follower (FVF) OCL-LDO with fast transient response. By adding a dynamic bias circuit to the FVF circuit, the proposed LDO has the ability to quickly adjust the gate voltage of the power transistor, without extra power consumption. The proposed LDO was designed in 0.18 μm CMOS process. The simulation results show that the recovery time is 52 ns when the load changes from 0.1 mA to 20 mA with a slew rate of 20 mA/ps, while the quiescent current is 92 μA with 1 V regulated output. The undershoot and overshoot voltage are 242 mV and 250 mV, respectively.