Abstract
This paper presents a multi-band low-noise amplifier (LNA) in the 45-nm CMOS silicon-on-insulator (SOI) process. The LNA consists of three stages, with the differential cascode amplifier as the core structure. The first stage is mainly responsible for input matching to ensure favourable noise characteristics and bandwidth, while the subsequent stages increase the gain. Moreover, the LNA utilizes baluns for input/output and interstage impedance matching. Switch capacitances are added to switch the three operating bands of the LNA, which cover 17–38 GHz overall. Measurement results show that the proposed LNA achieves a gain (S21) of 23.0 dB and a noise figure (NF) of 4.0 dB.
Funder
National Natural Science Foundation of China
Beijing Institute of Technology Research Fund Program for Young Scholars
Beijing Nova Program of Science and Technology
Subject
Electrical and Electronic Engineering,Computer Networks and Communications,Hardware and Architecture,Signal Processing,Control and Systems Engineering
Reference25 articles.
1. Millimeter-Wave Integrated Phased Arrays
2. A 2.99 dB NF 15.6 dB Gain 3-10GHz Ultra-wideband low-noise amplifier for UWB systems in 65 nm CMOS
3. A straightforward design technique for narrowband multi‐stage low‐noise amplifiers with I/O conjugate match
4. A 17.7–42.9-GHz Low Power Low Noise Amplifier with 83% Fractional Bandwidth for Radio Astronomical Receivers in 65-nm CMOS;AuChang;Proceedings of the Asia-Pacific Microwave Conference Proceedings,2020
5. A 2.5–31-GHz High Gain LNA in 0.15-μm GaAs pHEMT for Radio Astronomical Application;Lei;Proceedings of the Asia-Pacific Microwave Conference, Kyoto International Conference Center (ICC Kyoto),2018
Cited by
2 articles.
订阅此论文施引文献
订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献