Abstract
A multiplier is one of the main units for digital signal processing and communication systems. In this paper, a high speed and low complexity multiplier is designed on the basis of quantum-dot cellular automata (QCA), which is considered promising nanotechnology. We focus on Vedic multiplier architectures according to Vedic mathematics from ancient Indian sculptures. In fact, an adder is an important block in the design of almost all types of multipliers and a ripple carry adder is used to design simple multiplier implementations. However, a high-speed multi-bit multiplier requires high-speed adder owing to carry propagation. Cell-interaction-based QCA adders have better improvements over conventional majority-gate-based adders. Therefore, a two-bit Vedic multiplier is proposed in QCA and it is used to implement a four-bit form of the multiplier. The proposed architecture has a lower cell count and area compared to other existing structures. Moreover, simulation results demonstrate that the proposed design is sustainable and can be used to realize complex circuit designs for QCA communication networks.
Funder
National Research Foundation of Korea
Subject
Electrical and Electronic Engineering,Computer Networks and Communications,Hardware and Architecture,Signal Processing,Control and Systems Engineering
Cited by
32 articles.
订阅此论文施引文献
订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献