An Investigation of Clock Skew Using a Wirelength-Aware Floorplanning Process in the Pre-Placement Stages of MSV Layouts

Author:

Srinath B.,Verma Rajesh,Barnawi Abdulwasa Bakr,Raja Ramkumar,Muqeet Mohammed Abdul,Shukla Neeraj KumarORCID,Christy A. Ananthi,Bharatiraja C.ORCID,Munda Josiah LangeORCID

Abstract

Managing the timing constraints has become an important factor in the physical design of multiple supply voltage (MSV) integrated circuits (IC). Clock distribution and module scheduling are some of the conventional methods used to satisfy the timing constraints of a chip. In this paper, we propose a simulated annealing-based MSV floorplanning methodology for the design of ICs within the timing budget. Additionally, we propose a modified SKB tree representation for floorplanning the modules in the design. Our algorithm finds the optimal dimensions and position of the clocked modules in the design to reduce the wirelength and satisfy the timing constraints. The proposed algorithm is implemented in IWLS 2005 benchmark circuits and considers power, wirelength, and timing as the optimization parameters. Simulation results were obtained from the Cadence Innovus digital system taped-out at 45 nm. Our simulation results show that the proposed algorithm satisfies timing constraints through a 30.6% reduction in wirelength.

Funder

Deanship of Scientific Research at King Kha-lid University, Kingdom of Saudi Arabia

Publisher

MDPI AG

Subject

Electrical and Electronic Engineering,Computer Networks and Communications,Hardware and Architecture,Signal Processing,Control and Systems Engineering

Reference29 articles.

1. Low-power clock distribution using multiple voltages and reduced swings;Pangjun,2002

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