Latency-Optimized Design of Data Bus Inversion

Abstract

This paper proposes two new encoders for data bus inversion (DBI), which conventionally uses a majority voter to pick a data representation that minimizes switching activities and thus reduces the corresponding energy consumption. The new encoders employ simpler approximate voters comprising only two gate levels, which improve latency more than twice while still achieving switching activity savings by 9% and 11%, respectively. Although the proposed voters are not always accurate, the errors in the voters do not affect the correctness of data movement. We report various metrics, including latencies, areas, and operating powers, regarding five different designs, two proposed designs along with three conventional designs, based on 65-nm process implementations.