A 16 Bit 125 MS/s Pipelined Analog-to-Digital Converter with a Digital Foreground Calibration Based on Capacitor Reuse-Reference-Cited by-同舟云学术

A 16 Bit 125 MS/s Pipelined Analog-to-Digital Converter with a Digital Foreground Calibration Based on Capacitor Reuse

Published:2024-04-12 Issue:8 Volume:13 Page:1474
ISSN:2079-9292
Container-title:Electronics
language:en
Short-container-title:Electronics

Author:

Zhang Zhenwei¹^ORCID,Hu Yizhe¹²^ORCID,Lang Lili¹^ORCID,Dong Yemin¹²³^ORCID

Affiliation:

1. State Key Laboratory of Materials for Integrated Circuits, Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences, Shanghai 200050, China

2. University of Chinese Academy of Sciences, Beijing 100049, China

3. Center of Materials Science and Optoelectronics Engineering, University of Chinese Academy of Sciences, Beijing 100049, China

Abstract

A 16-bit 125 MS/s pipelined analog-to-digital converter (ADC) implemented in a 0.18 μm CMOS process is presented in this paper. A sample-and-hold amplifier-less (SHA-less) modified 2.5-bit front-end is adopted, which splits the sampling capacitor in half to eliminate the common-mode voltage buffer. The multiplying-digital-to-analog converter (MDAC) in the first pipeline stage is modified by reusing the sampling capacitor in a foreground digital calibration for improving the ADC linearity. This design can circumvent a dedicated reference buffer to generate the calibration voltages at all comparator thresholds. By calibrating the ADC in the digital domain, the integral non-linearity (INL) is improved from −9.2/10 LSB to −3/2.2 LSB, and the spurious-free dynamic range (SFDR) is optimized by over 8dB. The ADC consumes 154mW (reference buffer and clock included) from a 1.8 V supply.

Funder

Research Foundation of Strategic Priority Research Program of Chinese Academy of Sciences

Publisher

MDPI AG

Link

https://www.mdpi.com/2079-9292/13/8/1474/pdf

Reference27 articles.

1. An 800 MS/s Dual-Residue Pipeline ADC in 40 Nm CMOS;Vecchi;IEEE J. Solid-State Circuits,2011

2. Savla, A., Leonard, J., and Ravindran, A. (2004, January 23–26). A Novel Queuing Architecture for Background Calibration of Pipeline ADCs. Proceedings of the 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512), Vancouver, BC, Canada.

3. Sobhi, J., Kanani, Z.K., Tahmasebi, A., and Yousefi, M. (2009, January 25–27). A Mixed Mode Background Calibration Technique for Pipeline ADCs. Proceedings of the 2009 4th IEEE Conference on Industrial Electronics and Applications, Xi’an, China.

4. Sobhi, J., Kanani, Z.K., Tahmasebi, A., and Yousefi, M. (2009, January 3–5). A Simple Background Interstage Gain Calibration Technique for Pipeline ADCs. Proceedings of the 2009 6th International Conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology, Kuala Lumpur, Malaysia.

5. Lee, H.S., Hodges, D., and Gray, P. (1984, January 22–24). A self calibrating 12b 12 µs CMOS ADC. Proceedings of the 1984 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, San Francisco, CA, USA.