Dimensioning an FPGA for Real-Time Implementation of State of the Art Neural Network-Based HPA Predistorter

Abstract

Orthogonal Frequency Division Multiplexing (OFDM) is one of the key modulations for current and novel broadband communications standards. For example, Multi-band Orthogonal Frequency Division Multiplexing (MB-OFDM) is an excellent choice for the ECMA-368 Ultra Wideband (UWB) wireless communication standard. Nevertheless, the high Peak to Average Power Ratio (PAPR) of MB-OFDM UWB signals reduces the power efficiency of the key element in mobile devices, the High Power Amplifier (HPA), due to non-linear distortion, known as the non-linear saturation of the HPA. In order to deal with this limiting problem, a new and efficient pre-distorter scheme using a Neural Networks (NN) is proposed and also implemented on Field Programmable Gate Array (FPGA). This solution based on the pre-distortion concept of HPA non-linearities offers a good trade-off between complexity and performance. Some tests and validation have been conducted on the two types of HPA: Travelling Wave Tube Amplifiers (TWTA) and Solid State Power Amplifiers (SSPA). The results show that the proposed pre-distorter design presents low complexity and low error rate. Indeed, the implemented architecture uses 10% of DSP (Digital Signal Processing) blocks and 1% of LUTs (Look up Table) in case of SSPA, whereas it only uses 1% of LUTs in case of TWTA. In addition, it allows us to conclude that advanced machine learning techniques can be efficiently implemented in hardware with the adequate design.