Investigation of Source/Drain Recess Engineering and Its Impacts on FinFET and GAA Nanosheet FET at 5 nm Node

Abstract

Impacts of source/drain (S/D) recess engineering on the device performance of both the gate-all-around (GAA) nanosheet (NS) field-effect transistor (FET) and FinFET have been comprehensively studied at 5 nm node technology. TCAD simulation results show that the device off-leakage, including subthreshold leakage through the channel (Isub) and punch-through leakage (IPT) in the sub-channel, is strongly related to the S/D recess process. Firstly, device electrical characteristics such as current density distributions, On/Off-state current (Ion, Ioff), subthreshold swing (SS), RC delay, and gate capacitance (Cgg) are investigated quantitatively for DC/AC performance evaluation and comparison according to S/D lateral recess depth (Lrcs) variations. For both device types, larger Lrcs will result in a shorter effective channel length (Leff), so that the Ion and Ioff simultaneously increase. At the constant Ioff, the Lrcs can be optimized to enhance the device’s drivability by ~3% and improve the device’s RC delay by ~1.5% due to a larger Cgg as a penalty. Secondly, S/D over recess depth (Hrcs) in the vertical direction severely affects the punch-through leakage in the Sub-Fin or bottom parasitic channel region. The NSFET exhibits less Ioff sensitivity provided that it can be well controlled under 12 nm since the bottom parasitic channel is still gated. Furthermore, with both Hrcs and Lrcs accounted for in the device fabrication, the NSFET still shows better control of the off-leakage in the intrinsic and bottom parasitic channel regions and ~37% leakage reduction compared with FinFETs, which would be critical to enable further scaling and the low standby power application. Finally, the S/D recess engineering strategy has been given: a certain lateral recess could be optimized to obtain the best drive current and RC delay, while the vertical over-recess should be in tight management to keep the static power dissipation as low as possible.