Reduced-Complexity Tracking Algorithms on Chip for Real-Time Location Estimation

Author:

Chiou Yih-Shyh1ORCID,Chen Shih-Lun1ORCID,Chen Wei-Ting1

Affiliation:

1. Department of Electronic Engineering, Chung Yuan Christian University, No. 200 Chungpei Rd., Chungli District, Taoyuan City 320314, Taiwan

Abstract

This article puts forward a low-complexity filtering algorithm to achieve a low-complexity filtering chip design for real-time location tracking. In order to meet the need for low-complexity and real-time, the positioning tracking algorithm based on Kalman Filter (KF) is proposed. The KF itself has the functions of tracking, predicting, etc., which can correct the positioning into more accurate results. However, in the calculation of KF algorithms, each iteration often requires tedious and complex calculations of Kalman Gain (KG). Both software and hardware are very resource-intensive. Therefore, use the feature of KG in alpha-beta (α-β) filtering algorithm which can gradually balance in each iteration. Proposed a filtering algorithm that is based on low-complexity, low cost, and high efficiency. This algorithm uses DKF (Difference Kalman Filter) and PKF (Percentage Kalman Filter) depending on different environments. In other words, DKF and PKF are the algorithms which are generated based on different judging conditions. This algorithm can not only significantly reduce the time and the complexity of computing, but also greatly shorten the circuit area of the original algorithm. This algorithm has a large number of matrix operation. In the hardware calculation process, it solves matrix problems about hardware and then developed chip design. Coefficients are used by a multiple of 2 for operation. Use shifters instead of multipliers and dividers, significantly reducing complexity and circuit area. At the same time, deal with the problem of a floating-point number, achieve circuit function verification on the FPGA, and finally tape-out. The design uses the TSMC 0.18μm CMOS cell library provided by the TSRI, uses EDA to implement VLSI with the Design Vision of SYNOPSYS, the operating frequency of the circuit is 83.33 MHz, the value of gate counts is 22.84 K, the power consumption is 3.86 mW, and chip area is 582.63 μm × 580.23 μm.

Funder

Ministry of Science and Technology, Taiwan

Publisher

MDPI AG

Subject

Electrical and Electronic Engineering,Computer Networks and Communications,Hardware and Architecture,Signal Processing,Control and Systems Engineering

同舟云学术

1.学者识别学者识别

2.学术分析学术分析

3.人才评估人才评估

"同舟云学术"是以全球学者为主线,采集、加工和组织学术论文而形成的新型学术文献查询和分析系统,可以对全球学者进行文献检索和人才价值评估。用户可以通过关注某些学科领域的顶尖人物而持续追踪该领域的学科进展和研究前沿。经过近期的数据扩容,当前同舟云学术共收录了国内外主流学术期刊6万余种,收集的期刊论文及会议论文总量共计约1.5亿篇,并以每天添加12000余篇中外论文的速度递增。我们也可以为用户提供个性化、定制化的学者数据。欢迎来电咨询!咨询电话:010-8811{复制后删除}0370

www.globalauthorid.com

TOP

Copyright © 2019-2024 北京同舟云网络信息技术有限公司
京公网安备11010802033243号  京ICP备18003416号-3