Abstract
This paper proposes a new technique for implementing Finite State Machines (FSMs) in Field Programmable Gate Arrays (FPGAs). The proposed approach extends the called column compaction in two ways. First, it is applied to the state-encoding bits in addition to the outputs, allowing a reduction in the number of logic functions required both by the state transition function and by the output function. Second, the technique exploits the dedicated multiplexers usually included in FPGAs to increase the number of columns that can be compacted. Unlike conventional state-encoding techniques, the proposed approach reduces the number of logic functions instead of their complexity. An Integer Linear Programming (ILP) formulation that maximizes the number of compacted columns has been proposed. In order to evaluate the effectiveness of the proposed approach, experimental results using standard benchmarks are presented. In most cases, the proposed approach reduces the number of used Look-Up Tables (LUTs) with respect to the conventional FSM implementation.
Subject
Electrical and Electronic Engineering,Computer Networks and Communications,Hardware and Architecture,Signal Processing,Control and Systems Engineering
Reference29 articles.
1. Katz, R.H. (1994). Contemporary Logic Design, Benjamin/Cummings.
2. Barkalov, A., and Titarenko, L. (2009). Logic Synthesis for FSM-Based Control Units, Springer. Lecture Notes in Electrical Engineering.
3. Barkalov, A., Titarenko, L., Kolopienczyk, M., Mielcarek, K., and Bazydlo, G. (2016). Logic Synthesis for FPGA-Based Finite State Machines, Springer International Publishing.
4. Baranov, S. (2008). Logic and System Design of Digital Systems, TUT Press.
5. Barkalov, A., Titarenko, L., Mielcarek, K., and Chmielewski, S. (2020). Logic Synthesis for FPGA-Based Control Units, Springer.
Cited by
2 articles.
订阅此论文施引文献
订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献