Design of Synaptic Driving Circuit for TFT eFlash-Based Processing-In-Memory Hardware Using Hybrid Bonding
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Published:2023-01-29
Issue:3
Volume:12
Page:678
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ISSN:2079-9292
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Container-title:Electronics
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language:en
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Short-container-title:Electronics
Author:
Kim Younghee1, Jin Hongzhou1, Kim Dohoon1ORCID, Ha Panbong1ORCID, Park Min-Kyu2, Hwang Joon2ORCID, Lee Jongho2, Woo Jeong-Min3, Choi Jiyeon4ORCID, Lee Changhyuk4, Kwak Joon Young4ORCID, Son Hyunwoo3ORCID
Affiliation:
1. Department of Electronic Engineering, Changwon National University, Changwon 51140, Republic of Korea 2. Department of Electrical and Computer Engineering, Seoul National University, Seoul 08826, Republic of Korea 3. Department of Electronic Engineering, Engineering Research Institute (ERI), Gyeongsang National University, Jinju 52828, Republic of Korea 4. Korea Institute of Science and Technology (KIST), Seoul 02792, Republic of Korea
Abstract
This paper presents a synaptic driving circuit design for processing in-memory (PIM) hardware with a thin-film transistor (TFT) embedded flash (eFlash) for a binary/ternary-weight neural network (NN). An eFlash-based synaptic cell capable of programming negative weight values to store binary/ternary weight values (i.e., ±1, 0) and synaptic driving circuits for erase, program, and read operations of synaptic arrays have been proposed. The proposed synaptic driving circuits improve the calculation accuracy of PIM operation by precisely programming the sensing current of the eFlash synaptic cell to the target current (50 nA ± 0.5 nA) using a pulse train. In addition, during PIM operation, the pulse-width modulation (PWM) conversion circuit converts 8-bit input data into one continuous PWM pulse to minimize non-linearity in the synaptic sensing current integration step of the neuron circuit. The prototype chip, including the proposed synaptic driving circuit, PWM conversion circuit, neuron circuit, and digital blocks, is designed and laid out as the accelerator for binary/ternary weighted NN with a size of 324 × 80 × 10 using a 0.35 μm CMOS process. Hybrid bonding technology using bump bonding and wire bonding is used to package the designed CMOS accelerator die and TFT eFlash-based synapse array dies into a single chip package.
Funder
Institute of Information & communications Technology Planning & Evaluation
Subject
Electrical and Electronic Engineering,Computer Networks and Communications,Hardware and Architecture,Signal Processing,Control and Systems Engineering
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