General Methodology for the Design of Bell-Shaped Analog-Hardware Classifiers

Abstract

This study introduces a general methodology for the design of analog integrated bell-shaped classifiers. Each high-level architecture is composed of several Gaussian function circuits in conjunction with a Winner-Take-All circuit. Notably, each implementation is designed with modularity and scalability in mind, effectively accommodating variations in classification parameters. The operating principles of each classifier are illustrated in detail and are used in low-power, low-voltage, and fully tunable implementations targeting biomedical applications. The realization of this design methodology occurred within a 90 nm CMOS process, leveraging the Cadence IC suite for both electrical and layout design aspects. In the verification phase, post-layout simulation outcomes were meticulously compared against software-based implementations of each classifier. Through the simulation results and comparison study, the design methodology is confirmed in terms of accuracy and sensitivity.