Parallelism-Aware Channel Partition for Read/Write Interference Mitigation in Solid-State Drives
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Published:2022-12-06
Issue:23
Volume:11
Page:4048
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ISSN:2079-9292
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Container-title:Electronics
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language:en
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Short-container-title:Electronics
Author:
Lim Hyun Jo, Shin Dongkun, Han Tae HeeORCID
Abstract
The advancement of multi-level cell technology that enables storing multiple bits in a single NAND flash memory cell has increased the density and affordability of solid-state drives (SSDs). However, increased latency asymmetry between read and write (R/W) intensifies the severity of R/W interference, so reads cannot be processed for a long time owing to the extended flash memory resource occupancy of writing. Existing flash translation layer (FTL)-level mitigation techniques can allocate flash memory resources in a balanced manner taking R/W interference into account; however, due to the inefficient utilization of parallel flash memory resources, the effect on performance enhancement is restrictive. From the perspectives of the predicted access pattern and available concurrency of flash memory resources, we propose a parallelism-aware channel partition (PACP) scheme that prevents SSD performance degradation caused by R/W interference. Moreover, an additional performance improvement is achieved by reallocating interference-vulnerable page using leveraged garbage collection (GC) migration. The evaluation results showed that compared with the existing solution, PACP reduced the average read latency by 11.6% and average write latency by 6.0%, with a negligible storage overhead.
Funder
National R&D Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Science and ICT Ministry of Trade, Industry and Energy Institute of Information & Communications Technology Planning & Evaluation (IITP) funded by the Korea government MOTIE
Subject
Electrical and Electronic Engineering,Computer Networks and Communications,Hardware and Architecture,Signal Processing,Control and Systems Engineering
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