Analysis and Simulations of Hybrid Memory Scheme Based on Memristors

Abstract

The investigation of new memory schemes is significant for future generations of electronic devices. The purpose of this research is to present a detailed analysis of the processes in the memory elements of a memory section with memristors and isolating Metal Oxide Semiconductor (MOS) transistors. For the present analysis, a modified window function previously proposed by the author in another memristor model is used. The applied model is based on physical nonlinear current-voltage and state-voltage characteristics. It is suitable for illustration of the processes in the memristors for both writing and reading procedures. The memory scheme is simulated using a nonlinear drift model with an improved window function. The used model was previously adjusted according to the reference Pickett model. The memory circuit is analyzed for writing and reading information procedures. The memristor current-voltage relationship is compared to physical experimental characteristics and to results acquired by the use of basic window functions. A satisfactory coincidence between the corresponding results is established. For the used logical signals, the memory elements operate in a state near to hard-switching mode. It is confirmed that the memristor model with a modified window function applied here is suitable for investigating complex memristor circuits for a general operating mode.