Noise Reduction of Atomic Force Microscopy Measurement Data for Fitting Verification of Chemical Mechanical Planarization Model

Author:

Ren Bowen1ORCID,Chen Lan2ORCID,Chen Rong2ORCID,Ji Ruian2,Wang Yali2

Affiliation:

1. The EDA Center, Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China

2. The School of Electronic, Electrical and Communication Engineering, University of Chinese Academy of Sciences, Beijing 100049, China

Abstract

In advanced integrated circuit manufacturing processes, the quality of chemical mechanical flattening is a key factor affecting chip performance and yield. Therefore, it has become increasingly important to develop an accurate predictive model for the chip surface topography after chemical mechanical flattening. In the modeling process, the noise problem of atomic force microscopy measurement data is relatively serious. To solve this problem, the noise characteristics of atomic force microscope measurement data for chip surface topography in this field are studied and discussed in this paper. It is found that the noise present in such problems is mainly triggered by the vibration and tilt of the probe. Two types of noise, low-frequency and high-frequency, are presented in the time domain. In order to solve the noise problem in this modeling data, this paper analyzes the spectral characteristics of the measurement data using Fourier transform, and a wavelet-Fourier transform composite noise reduction process is proposed. The algorithm is applied to the noise reduction of the chip surface data of 32 nm copper interconnect process. The noise reduction results were compared with scanning electron microscope photographs to verify the effectiveness of the noise reduction.

Funder

Foundation for Research on intelligent EDA tool

Publisher

MDPI AG

Subject

Electrical and Electronic Engineering,Computer Networks and Communications,Hardware and Architecture,Signal Processing,Control and Systems Engineering

Reference33 articles.

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3. Tugbawa, T.E., Park, T.H., and Boning, D.S. (2002, January 5). Integrated chip-scale simulation of pattern dependencies in copper electroplating and copper chemical mechanical polishing processes. Proceedings of the IEEE 2002 International Interconnect Technology Conference (Cat. No.02EX519), Burlingame, CA, USA.

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5. Ghulghazaryan, R., Wilson, J., and Abouzeid, A. (October, January 30). FEOL CMP modeling: Progress and challenges. Proceedings of the 2015 International Conference on Planarization/CMP Technology, Chandler, AZ, USA.

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