Abstract
This paper presents an analysis of the influence of parasitic inter-electrode capacitances of the components of logarithmic analogue-to-digital converters with successive approximation with a variable logarithm base. Mathematical models of converter errors were developed and analyzed taking into account the parameters of modern components. It has been shown that to achieve satisfactory accuracy for the 16 bit LADC, the capacitance of the capacitor cell must not be less than 10 nF; for the 12 bit LADC, 1 nF is sufficient.
Funder
Kielce University of Technology
Subject
Electrical and Electronic Engineering,Computer Networks and Communications,Hardware and Architecture,Signal Processing,Control and Systems Engineering
Cited by
5 articles.
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