An Efficient Reduction of Timer Interrupts for Model Checking of Embedded Assembly Programs

Abstract

In verifying programs for embedded systems, it is essential to reduce the verification time because state explosion may occur during model checking. One solution is to reduce the number of interrupt handler executions. In particular, when periodic interrupts such as timer interrupts are incorporated, it is necessary to know the physical time. In this paper, we define a control flow automaton (CFA) that can handle time and propose an algorithm based on interrupt handler execution reduction (IHER). The proposed method reduces the number of interrupt executions, including timer interrupts. A case study verified the effectiveness of this algorithm.