Design of a 12-Bit SAR ADC with Calibration Technology

Abstract

Successive approximation register (SAR) analog-to-digital converters (ADC) have the advantages of a simple structure, low power consumption and a small area compared with other types of ADCs, and thus, high-performance SAR ADCs have always been a hot research topic in the industry. In this paper, a 12-bit SAR ADC design with calibration using a hybrid RC digital-to-analog converter(RC DAC) structure is proposed to improve the conversion accuracy of the ADC and reduce the circuit area at the same time. The analog supply voltage and reference voltage of the ADC are 3.3 V, and the digital supply voltage is 1.2 V. The ADC adopts a mixed digital–analog design scheme, in which the internal comparator, latch, DAC capacitor array, etc., are analog parts, and the rest of the SAR algorithms and calibration algorithms are all implemented in digital Verilog code, with a conversion accuracy of 0.8 mV and a calibration accuracy of 0.5 LSB. The ADC can be selectively calibrated, and the simulation shows that the accuracy of the calibrated ADC can be guaranteed to be within 2 LSB under a 14 MHz digital clock with a sampling rate of 1 MHz. After simulation at a sampling rate of 1 MHz and an input frequency of 244 Hz sine wave, the effective bit count of the ADC is 9.54 bits and the SFDR is 63.71 dB. The circuit consumes 1.78 mW with a 3.3 V supply voltage. The overall layout core area is 411 μm × 517 μm.