Analysis and Optimization Design Scheme of CMOS Ultra-Wideband Reconfigurable Polyphase Filters on Mismatch and Voltage Loss
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Published:2024-02-05
Issue:3
Volume:13
Page:658
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ISSN:2079-9292
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Container-title:Electronics
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language:en
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Short-container-title:Electronics
Author:
Wang Yingze1, Li Xiaoran1234ORCID, Wang Yuanze1, Wang Xinghua1234, Liu Zicheng3, Han Fang4ORCID, Qi Quanwen4ORCID
Affiliation:
1. School of Integrated Circuits and Electronics, Beijing Institute of Technology, Beijing 100081, China 2. Advanced Technology Research Institute, Beijing Institute of Technology, Jinan 250101, China 3. BIT Chongqing Institute of Microelectronics and Microsystems, Chongqing 401332, China 4. Yangtze Delta Region Academy of Beijing Institute of Technology, Jiaxing 314000, China
Abstract
This manuscript presents an analysis and optimization scheme for the ultra-wideband passive reconfigurable polyphase filters (PPFs) to minimize I/Q (in-phase and quadrature-phase) phase/amplitude mismatch and voltage loss. By building a mathematical model of the voltage transfer, the relationship between the resonant frequency of each stage and the I/Q mismatch and the relationship between the network impedance and the voltage loss are revealed, providing a scheme for PPF optimization. The proof-of-concept 2~8 GHz wideband reconfigurable PPF is designed in a 55 nm CMOS process. The optimization scheme enables the designed PPF to achieve an I/Q phase mismatch within 0.2439° and an I/Q amplitude mismatch within 0.098 dB throughout the entire band, and it shows great robustness during Monte Carlo sampling. The maximum voltage loss is 17.7 dB, and the total chip area is 0.174 × 0.145 mm2.
Funder
Beijing Institute of Technology Research Fund Program for Young Scholars National Natural Science Foundation of China
Subject
Electrical and Electronic Engineering,Computer Networks and Communications,Hardware and Architecture,Signal Processing,Control and Systems Engineering
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