OctoFAS: A Two-Level Fair Scheduler that Increases Fairness in Network-Based Key-Value Storage

Author:

Park Yeohyeon1,Park Junhyeok1,Park Junghwan1,Khan Awais2,Kim Kyeongpyo3,Park Sung-Soon34,Kim Youngjae1ORCID

Affiliation:

1. Department of Computer Science and Engineering, Sogang University, Seoul 04107, Republic of Korea

2. Oak Ridge National Laboratory, Oak Ridge, TN 37831, USA

3. GlueSys Co., Ltd., Anyang 14055, Republic of Korea

4. Department of Computer Science and Engineering, Anyang University, Anyang 14028, Republic of Korea

Abstract

We identified a fairness problem in a network-based key-value storage system using Intel Storage Performance Development Kit (SPDK) in a multitenant environment. In such an environment, each tenant’s I/O service rate is not fairly guaranteed compared to that of other tenants. To address the fairness problem, we propose OctoFAS, a two-level fair scheduler designed to improve overall throughput and fairness among tenants. The two-level scheduler of OctoFAS consists of (i) inter-core scheduling and (ii) intra-core scheduling. Through inter-core scheduling, OctoFAS addresses the load imbalance problem that is inherent in SPDK on the storage server by dynamically migrating I/O requests from overloaded cores to underloaded cores, thereby increasing overall throughput. Intra-core scheduling prioritizes handling requests from starving tenants over well-fed tenants within core-specific event queues to ensure fair I/O services among multiple tenants. OctoFAS is deployed on a Linux cluster with SPDK. Through extensive evaluations, we found that OctoFAS ensures that the total system throughput remains high and balanced, while enhancing fairness by approximately 10% compared to the baseline, when both scheduling levels operate in a hybrid fashion.

Funder

Institute of Information Communications Technology Planning Evaluation

Office of Science of the U.S. Department of Energy

Publisher

MDPI AG

Subject

Electrical and Electronic Engineering,Computer Networks and Communications,Hardware and Architecture,Signal Processing,Control and Systems Engineering

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