Scalable Hardware-Efficient Architecture for Frame Synchronization in High-Data-Rate Satellite Receivers

Author:

Crocetti Luca1ORCID,Pagani Emanuele12ORCID,Bertolucci Matteo2ORCID,Fanucci Luca1ORCID

Affiliation:

1. Department of Information Engineering, University of Pisa, Via G. Caruso 16, 56122 Pisa, Italy

2. IngeniArs S.r.l., Via Ponte a Piglieri 8, 56121 Pisa, Italy

Abstract

The continuous technical advancement of scientific space missions has resulted in a surge in the amount of data that is transferred to ground stations within short satellite visibility windows, which has consequently led to higher throughput requirements for the hardware involved. To aid synchronization algorithms, the communication standards commonly used in such applications define a physical layer frame structure that is composed of a preamble, segments of modulation symbols, and segments of pilot symbols. Therefore, the detection of a frame start becomes an essential operation, whose accuracy is undermined by the large Doppler shift and quantization errors in hardware implementations. In this work, we present a design methodology for frame synchronization modules that are robust against large frequency offsets and rely on a parallel architecture to support high throughput requirements. Several algorithms are evaluated in terms of the trade-off between accuracy and resource utilization, and the best solution is exemplified through its application to the CCSDS 131.2-B-1 and CCSDS 131.21-O-1 standards. The implementation results are reported for a Xilinx KU115 FPGA, thereby showing the capability of supporting baud rates that are greater than 2 Gbaud, as well as a corresponding throughput of 15.80 Gbps. To the best of our knowledge, this paper is the first to propose a design methodology for parallel frame synchronization modules that has applicability to the CCSDS 131.2-B-1 and CCSDS 131.21-O-1 standards.

Funder

IngeniArs S.r.l.

Italian Ministry of University and Research

Publisher

MDPI AG

Reference31 articles.

1. CCSDS (2012). Flexible Advanced Coding and Modulation Scheme for High Rate Telemetry Applications, CCSDS Secretariat, National Aeronautics and Space Administration. Recommended Standard CCSDS 131.2-B-1 (Blue Book).

2. Lamoral Coines, A., and Jiménez, V.P.G. (2021). CCSDS 131.2-B-1 transmitter design on FPGA with adaptive coding and modulation schemes for satellite communications. Electronics, 10.

3. Next Generation High-Rate Telemetry;Ugolini;IEEE J. Sel. Areas Commun.,2018

4. CCSDS (2021). Serially Concatenated Convolutional Codes-eXtension (SCCC-X), CCSDS Secretariat, National Aeronautics and Space Administration. Experimental Specification CCSDS 131.21-O-1 (Orange Book).

5. State-of-the-art space mission telecommand receivers;Baldi;IEEE Aerosp. Electron. Syst. Mag.,2017

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