Affiliation:
1. Faculty of Applied Energy System, Electronic Engineering Major, Jeju National University, Jeju 63243, Republic of Korea
Abstract
The conventional address map often incurs traffic congestion in on-chip memory components and degrades memory utilization when the access pattern of an application is not matched with the address map. To reduce traffic congestion and improve the memory system performance, we propose an adaptive image size padding technique for a given address mapping and a hardware configuration. In the presented software approach, the system can adaptively determine the image pad size at the application-invoke time to enhance the load balancing across the on-chip memory hierarchy. Mainly targeting a high-bandwidth image processing application running in a device accelerator of an embedded system, we present the design, describe the algorithm, and conduct the performance experiment. As a result, the experiments indicate the presented design can improve load balancing up to 95% and performance up to 35%, with insignificant memory footprint overheads.
Subject
Electrical and Electronic Engineering,Computer Networks and Communications,Hardware and Architecture,Signal Processing,Control and Systems Engineering
Reference30 articles.
1. Breaking address mapping symmetry at multi-levels of memory hierarchy to reduce DRAM row-buffer conflicts;Zhang;J. Instr.-Level Parallelism,2001
2. Kaseridis, D., Stuecheli, J., and John, L.K. (2011, January 3–7). Minimalist open-page: A DRAM page-mode scheduling policy for the many-core era. Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture, Porto Alegre, Brazil.
3. Shao, J., and Davis, B.T. (2005). Workshop on Software and Compilers for Embedded Systems, Association for Computing Machinery.
4. Wei, R., Li, C., Chen, C., Sun, G., and He, M. (2021). Memory access optimization of a neural network accelerator based on memory controller. Electronics, 4.
5. Wang, M., Zhang, Z., Cheng, Y., and Nepal, S. (2020, January 20–24). Dramdig: A knowledge-assisted tool to uncover dram address mapping. Proceedings of the 2020 57th ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, USA.