A 22.3-Bit Third-Order Delta-Sigma Modulator for EEG Signal Acquisition Systems

Abstract

This paper presents a high resolution delta-sigma modulator for continuous acquisition of electroencephalography (EEG) signals. The third-order single-loop architecture with a 1-bit quantizer is adopted to achieve 22.3-bit resolution. The effects of thermal noise on the performance of the delta-sigma modulator are analyzed to reasonably allocate the switched-capacitor sizes for optimal signal to noise ratio (SNR) and minimum chip area. The coefficients in feedback path and input path are optimized to avoid the signal distortion under the full-scale input voltage range with almost no increase in total capacitance sizes. Fabricated in 0.5 µm CMOS technology and powered by a 5 V voltage supply, the proposed delta-sigma modulator can achieve 136 dB peak SNR with 16 Hz input and 137 dB dynamic range in 100 Hz signal bandwidth with an oversampling ratio of 512. The modulator dissipates 700 µA. The core chip area is 1.96 mm2. The modulator occupies 1.41 mm2 and the decimator occupies 0.55 mm2.