A 5.67 ENOB Vector Matrix Multiplier with Charge Storage FET Cells and Non-Linearity Compensation Techniques

Abstract

In this paper, we provide a thorough analysis and enhancement techniques of the linearity between the input voltage and output current in charge storage field effect transistor (FET) cells for a vector–matrix multiplier array in neural networks. A planar floating gate FET cell revealed superior linearity, because of boosting the floating gate using a drain voltage through capacitive coupling. If the coupling capacitance is extended by up to half of the gate capacitance, the coefficient of determination for linear regression is easily greater than 99.5%. However, the linearity of the charge trap FET, which keeps electrons in the insulating gate dielectric, must be compensated by either boosting the drain voltage, using a non-linear input driver, or supplying a quadratic current through an auxiliary path in the cell. Drain voltage boosting is limitedly effective over a small input range, while the auxiliary current path shows a coefficient of determination greater than 99.5% over a 500 mV input range. If the cell area matters, the charge trap FET with a diode connected FET as an auxiliary current path revealed the best performance, with an effective number of bits of 5.67, in a 21.3 F2 cell area.