Affiliation:
1. School of Microelectronics and School of Integrated Circuits, Nantong University, Nantong 226001, China
2. College of Integrated Circuit Science and Engineering, Nanjing University of Posts and Telecommunications, Nanjing 210023, China
Abstract
In this study, we introduce a stagger-stacked DDR module that comprises one IPD chip (top die) along with four memory chips initially. The steady-state thermal characteristics of this configuration were empirically assessed using a dedicated thermal test vehicle. The purpose of this research is to investigate the module’s junction temperature by adjusting four factors: the thermal conductivity of the molding plastic, chip thickness, chip misalignment length, and the thermal conductivity of the adhesive film. We observed that the junction temperature decreases with an increase in the chip staggered length. An improved orthogonal experimental method was utilized to achieve the optimal design of the module. The optimal junction temperature has decreased by 4.74% compared to the initial value. Additionally, three alternative packaging technologies—cantilever, pyramid, and a combination of cantilever and pyramid—were evaluated for the benchmarking of the thermal performance. Ultimately, the stagger-stacked package demonstrated a reduction in the junction temperature by 3.62%, 7.95%, and 5.63%, respectively, when compared to the three traditional stacked packages.
Funder
National Natural Science Foundation of China
Reference15 articles.
1. Heat Dissipation Capability of a Package-on-Package Embedded Wafer-Level Package;Han;IEEE Des. Test,2015
2. Han, Y., Zheng, B., Choong, C.S., Jung, B.Y., and Zhang, X. (2013, January 11–13). Package-level thermal management of a 3D embedded wafer level package. Proceedings of the 2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013), Singapore.
3. Hsieh, C., Wu, C., and Yu, D. (June, January 31). Analysis and Comparison of Thermal Performance of Advanced Packaging Technologies for State-of-the-Art Mobile Applications. Proceedings of the IEEE 66th Electronic Components and Technology Conference (ECTC), Las Vegas, NV, USA.
4. Oprins, H., and Beyne, E. (2019, January 28–31). Thermal Analysis of a 3D Flip-chip Fan-out Wafer Level Package (fcFOWLP) for High Bandwidth 3D Integration. Proceedings of the 18th IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm), Las Vegas, NV, USA.
5. Optimization of the thermal reliability of a four-tier die-stacked SiP structure using finite element analysis and the Taguchi method;Tang;Microelectron. J.,2018